G-Research is Europe’s leading quantitative finance research firm. We hire the brightest minds in the world to tackle some of the biggest questions in finance. We pair this expertise with machine learning, big data, and some of the most advanced technology available to predict movements in financial markets.
This role is based in G-Research’s office in Dallas. Opened in 2022, the Dallas office is a key infrastructure hub where we work on the latest cloud technologies in a cutting-edge environment.
The role
The Low Latency Engineering Group is responsible for a low-latency system that is a critical part of a global investment platform. The group includes teams responsible for market-data, order-entry and order-execution functions.
The group has many years of experience in building low-latency software and is now building its first FPGA-based platform. We are applying modern engineering techniques (continuous delivery, fast feedback, and collaborative development practises using git) to FPGA development. We are looking for an experienced FPGA engineer, with strong hardware skills, to help us do this.
The LLE FPGA team is a small hybrid team of software and hardware engineers. The team is responsible for its own QA, tooling and continuous delivery pipelines. We value flexibility and willingness to collaborate on the problems we work on.
Key responsibilities of the role include:
- Developing RTL HDL in SystemVerilog and VHDL
- Writing automated test benches
- Writing scripts in Python
- Developing some software in C/C++
- Building Continuous Delivery pipelines for all components
We give people time to learn and develop – including one day a fortnight to work on your own ideas and the opportunity to attend training and conferences.
Who are we looking for?
You will be an enthusiastic and capable Engineer who is able to solve real-world problems in HDL and software. You should be flexible and pro-active, with the ability to make complex systems work and to debug them when they don’t. You should enjoy working as part of a collaborative engineering team.
The ideal candidate will have the following skills and experience:
- Practical experience of hardware/software co-design for FPGA-based systems
- HDL development skills in one of SystemVerilog, Verilog or VHDL
- System analysis and debugging skills
- Experience of working in a collaborative engineering team, preferably using a git-based development workflow, such as GitHub
- Some software development skills in C or C++
- Basic knowledge of Python
- The ability to communicate well with technical and non-technical people
Why should you apply?
- Market-leading compensation plus annual discretionary bonus
- Informal dress code and excellent work/life balance
- 25 days of paid time off, including Summer Fridays
- Sick days, military leave, and family and medical leave
- Generous 401(k) plan
- 12-weeks’ fully paid parental leave
- Medical and Prescription, Dental, and Vision insurance
- Life and Accidental Death & Dismemberment (AD&D) insurance
- Employee Assistance and Wellness programs
- Generous relocation allowance and support
- Great selection of office snacks, and hot & cold drinks
- On-site gym and car park
G-Research is committed to cultivating and preserving an inclusive work environment. We are an ideas-driven business and we place great value on diversity of experience and opinions.
We want to ensure that applicants receive a recruitment experience that enables them to perform at their best. If you have a disability or special need that requires accommodation please let us know in the relevant section.